As semiconductor technology sizes are reduced, shallow trench isolation (STI) has become a preferable choice for electrical isolation. As current research shows, STI stress has significant impacts on complementary metal oxide semiconductor (CMOS) device performance. For example, STI stress may cause strain in channel regions of adjacent devices (referred to as strained devices) such that electrical characteristics of the devices will be modified. As is known in the art, STI stress that enhances one type of device, e.g., N-channel field effect transistor (nFET), would degrade the other type of device, e.g., P-channel field effect transistor (pFET). For example, tensile STI stress will increase on-current (Ion) of an nFET by increasing electron mobility such that performance of a pFET will be enhanced. However, tensile STI stress will have the opposite effect on a nearby pFET by reducing hole mobility and hence decreasing Ion of the pFET. In a conventional CMOS circuit, e.g., circuit 10 of FIG. 1, nFET 12 and pFET 14 are separated by STI 16 on the same silicon layer (substrate) 18. As such, effects of STI 16 stress on conventional CMOS circuit 10 are always mixed, i.e., enhancing one type of device, e.g., nFET 12, while degrading the other type of device, e.g., pFET 14, regardless of the type of stress.
In addition, different types of liner stress are known to have different effects on the FET performance. One approach to this problem proposes a dual stress liner to improve both nFET and pFET performance. However, formation of dual stress liner requires multiple deposition and etching of liner films from the FETs in the presence of a silicide, which may seriously affect the silicide sheet resistance value.
In view of the foregoing, there is a need in the art for a solution to solve the above identified problems and take the full advantages of strained MOSFETs.